MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202621050060 A) filed by Indian Institute Of Technology, Bhilai on April 20, 2026, for Voronoi Tessellation System And Method For Grain Modeling In Ferroelectric Capacitors For Nonvolatile Memories.
Inventors include Chauhan, Nitanshu; Sampath, Bellala Sai; Kai Ni; and Yadav, Sarita.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: The present invention provides a grain structure modeling system (100) for a cylindrical ferroelectric capacitor, including a grain center generation module (102) configured to determine a number of grains based on surface area of a ferroelectric layer region and a grain size parameter, and to generate grain center coordinates within the ferroelectric layer region. A Voronoi tessellation module (104) receives the grain center coordinates and performs Voronoi tessellation to generate a three- dimensional grain structure having polyhedral grains. A geometry extraction module (106) processes the Voronoi tessellation output to extract grain geometry data including vertices, edges, and faces with connectivity information. A grain construction module (108) receives the extracted geometry data and constructs the polyhedral grains in a device simulation environment. The generated polyhedral grains are randomly designated as dielectric within ferroelectric matrix for creating the mixed ferroelectric-dielectric phase structure. Thus, the methodology enables realistic modeling of ferroelectric capacitors for non-volatile memory applications. (Figure 2)
Disclaimer: Curated by HT Syndication.
