MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202641087871 A) filed by Vellore Institute Of Technology on July 17, 2026, for Vertically Integrated Fefet-Nanosheet Synaptic Device For Neuromorphic Computing.
Inventors include Kannam Sai Lakshmi Prasanth; and Rajan Kumar Pandey.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: ABSTRACT VERTICALLY INTEGRATED FEFET-NANOSHEET SYNAPTIC DEVICE FOR NEUROMORPHIC COMPUTING A synaptic device (100) comprises a ferroelectric field-effect transistor (200) configured to store a non-volatile synaptic weight, the ferroelectric field-effect transistor (200) comprising a ferroelectric layer (212), a channel (220), a gate electrode (210), a source terminal (230), and a drain terminal (240). A dual-gate nanosheet transistor (300) positioned below the ferroelectric field-effect transistor (200) comprises a nanosheet channel (310), a source region (320) and a drain region (330) at opposite ends of the nanosheet channel (310), a primary gate (340) adjacent to the source region (320), and a secondary gate (350) adjacent to the drain region (330), wherein the primary gate (340) and secondary gate (350) are separated by a dielectric spacer (360). A local via (400) electrically connects the drain terminal (240) to the secondary gate (350), wherein the local via (400) is contained within a footprint of the synaptic device (100). (Fig. 1)
Disclaimer: Curated by HT Syndication.
