MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641110058 A) filed by Vellore Institute Of Technology on September 14, 2026, for Verification-Gated Machine Unlearning For Language Model Synchronization.
Inventors include Dr M Rajasekhara; Dhanush Konduru; and Dr Nirmala M.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: ABSTRACT VERIFICATION-GATED MACHINE UNLEARNING FOR LANGUAGE MODEL SYNCHRONIZATION A computer-implemented method for synchronizing a language model (120) with a versioned dataset includes receiving, by a dataset version differ (110), a first dataset version and a second dataset version, each dataset version comprising a plurality of records; computing a record-level difference to generate an added record set, a removed record set, and a retained record set; learning, by a memorization trainer (130), the added record set on the language model (120) without full retraining; unlearning, by a retain-anchored unlearner (140), the removed record set while anchoring the retained record set; performing, by a multi-probe behavioral audit module (150), a behavioral audit by interrogating each entity in the removed record set through a plurality of paraphrased probes and applying a value-based leak detector; computing a Trust score as a harmonic mean of a ForgetScore and a UtilityScore; performing, by a relearning-resistance gate (160), a relearning-resistance test measuring a recovered fraction relative to an oracle benchmark (180); and accepting the language model (120) for release when the Trust score is at least a first threshold and the recovered fraction is at most a second threshold, or flagging records that fail verification.
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