MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202641086203 A) filed by Indian Institute Of Technology Madras Iit Madras on July 14, 2026, for Timing Side Channel Attack Mitigation In Speculative Memory Dependency Resolution.
Inventors include Veezhinathan, Kamakoti; Srinivasan, Gopalakrishnan; Subramanian, Gayathri; and Palani, Girinath.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: ABSTRACT TIMING SIDE CHANNEL ATTACK MITIGATION IN SPECULATIVE MEMORY DEPENDENCY RESOLUTION 5 Example approaches for mitigating timing side-channel attacks in a processor are described. An example approach includes generating a random mask selecting a subset of a plurality of physical address bits for use in memory dependence prediction. The example approach further includes applying the random mask to a physical address associated with a store 10 operation to produce a masked physical address for storage in a store address buffer entry. During speculative execution of a load operation, the random mask is applied to a physical address associated with the load operation to generate a masked load address. The masked load address is compared with the masked physical address to determine a potential 15 dependency between the load operation and the store operation. Execution of the load operation is selectively controlled based on the comparison.
Disclaimer: Curated by HT Syndication.
