MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641110718 A) filed by Ms. C. Subha Priyadharshini; Dr. G. Puvaneswari; Dr. B. Premalatha; Dr. B. Bhuvaneshwari; Ms. V. Gowri Priyaa; Ms. V. Sowmya; V Ramji; S Madhankumar; and AG Gurrudarshani on September 15, 2026, for Task-Aware Low-Power Risc-V Processor Core And Controlling Method Thereof.
Inventors include Ms. C. Subha Priyadharshini; Dr. G. Puvaneswari; Dr. B. Premalatha; Dr. B. Bhuvaneshwari; Ms. V. Gowri Priyaa; Ms. V. Sowmya; V Ramji; S Madhankumar; and AG Gurrudarshani.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: A task-aware low-power RISC-V processor core (100) comprises a RISC-V processing unit (102) configured to execute instructions associated with one or more processor tasks. A custom instruction decoding unit (104) identifies a customizable SLEEP instruction and generates a SLEEP request for initiating transition toward a low-power state. An instruction completion monitoring unit (106) verifies completion of active instructions, while a task-aware sleep controller (108) authorizes entry into the low-power state only upon verification of a safe sleep condition. A sleep state (FSM) (110) controls transitions between active, sleep-request, instruction- completion verification, and low-power sleep states. A core low-power control unit (112) reduces operational activity of processor functional blocks, while a wake-up logic unit (114) initiates transition toward the active state upon detecting a wake-up signal. A processor state retention unit (116) maintains execution state for resumption of operation, thereby reduci
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