MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202647114771 A) filed by Xilinx, Inc. on September 25, 2026, for System-Level Data Compression Scheme.
Inventors include Srinivasan, Krishnan; and Song, Zhiye.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: An implementation includes an integrated circuit, a network-on-chip (NoC) a plurality of first circuits, each first circuit may include a compressor and a decompressor, the compressor being configured to compress datastreams, and the decompressor being configured to decompress the compressed datastreams, the compressed datastreams may include symbols, the decompressor may include a plurality of symbol decoders configured to decode in parallel the compressed datastreams. The integrated circuit also includes a memory circuit. The circuit also includes a plurality of switches, the plurality of switches being interconnected and communicatively linking the plurality of first circuits with the memory circuit.
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