MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641111184 A) filed by Vellore Institute Of Technology, Chennai on September 16, 2026, for System For Compressing Multiple Binary Input Signals.
Inventors include Renumanjari R K; Sherlin Immanuela R; Haritra G; and Umadevi S.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: The present disclosure relates to a system (100) for compressing multiple binary input signals. The system (100) includes a plurality of input nodes (101) configured to receive seven single-bit input signals and a compression module (102, 104) operatively coupled to the input nodes (101). The compression module (102, 104) is configured to generate three output signals (S0, S1, S2) corresponding to weighted binary significance of the input signals. The compression module may be implemented in accordance with a hierarchical multi-stage compression architecture (102) or a propagate-generate multiplexer-based compression architecture (104) The hierarchical architecture utilizes a two-stage compression mechanism with parallel processing of input subsets to generate intermediate sums and carries, followed by combination to produce final outputs. The propagate-generate architecture employs partial compression, propagate-generate logic, and multiplexer-based carry selection for efficient output generation. The system achieves reduced delay, lower power consumption, and improved power-delay performance for high-speed arithmetic applications.
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