MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641073914 A) filed by Mohan Babu University on June 15, 2026, for System And Method For High-Speed Multiplier Design Using Stacker-Based Binary Compressors And Vedic Multiplication Algorithm.
Inventors include Mr M. Ventaka Naresh; and Mr. G. Naresh.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: The present invention relates to a multiplier architecture designed for high-speed digital arithmetic operations. Multipliers are widely used in applications such as digital signal processing, machine learning, image processing, and embedded computing systems. The proposed design integrates the Urdhva Tiryagbhyam multiplication algorithm from Vedic mathematics with stacker-based binary compressors to improve multiplier performance. The Urdhva Tiryagbhyam algorithm enables parallel generation of partial products, which significantly reduces computation delay. These partial products are then processed using binary compressors such as 6:3 and 7:3 compressors to reduce the number of partial product rows. Approximate compressors may also be used to simplify logic operations and reduce hardware complexity. The reduced partial products are combined using efficient adder circuits to produce the final multiplication result. The multiplier architecture is implemented using Verilog hardware description language and synthesized using FPGA development tools. Experimental results demonstrate improvements in speed, power efficiency, and area utilization compared to conventional multiplier designs. The proposed architecture provides an efficient solution for implementing multiplication operations in modern digital systems.
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