MUMBAI, India, Aug. 24 -- Intellectual Property India has published a patent application (202641097687 A) filed by Ms. G. Sri Vidya; and Dr. G. Devadasu on August 12, 2026, for System And Method For Hardware-Assisted Adaptive Memory Consistency Enforcement Using Runtime Conflict Prediction In Distributed Shared-Memory Systems.
Inventors include Dr. S. Siva Skandha; Mr. A. Vivekanand; Dr. R. Venkateswara Reddy; Ms. K. Archana; Mr. D. Mohan; and Dr V Narasimha.
The application for the patent was published on August 21, 2026, under issue no. 34/2026.
Abstract: The present invention discloses a system (100) and method for hardware-assisted adaptive memory consistency enforcement in distributed shared-memory systems. The system (100) comprises a memory (102), a processor (104), and a communication module (106) configured to communicate with distributed processing nodes. The processor (104) cooperates with an access monitoring module (108), a hardware telemetry acquisition module (110), an access dependency analysis module (112), a conflict prediction module (114), an adaptive consistency control module (116), a synchronization optimization module (118), and a runtime policy update module (120). The disclosed system dynamically monitors runtime memory access operations and hardware-derived telemetry data to identify predicted memory conflict conditions associated with concurrent shared memory transactions. Based on the predicted conflict conditions, the system adaptively modifies memory consistency enforcement policies and synchronization operations to reduce synchronization overhead, cache coherence traffic, memory contention, and inter-node latency while maintaining distributed memory consistency and improving computational scalability. Fig.1
Disclaimer: Curated by HT Syndication.
