MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641073782 A) filed by Vellore Institute Of Technology on June 14, 2026, for System And Method For Energy Efficient Processor Execution Using Ml Based Hazard Detection And Performance Counters.
Inventors include Konatham Sumalatha; Shann Antony Suresh; and Aditya P Bhimani.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: A machine learning-based system and method for automatic detection and analysis of processor pipeline hazards to enable energy-efficient software execution. The system comprises an execution profiling module to collect microarchitectural performance metrics from a performance monitoring unit, and an energy measurement module to measure processor and memory energy consumption using running average power limit (RAPL) hardware counters. A feature engineering module generates structured execution records by correlating performance metrics with energy consumption and computing derived behavioral indicators. A hazard labeling module categorizes these records into distinct pipeline hazard classes to train a supervised machine learning model. During inference, the trained model predicts a dominant pipeline hazard class for a new program execution. An explainability module applies feature attribution to determine the contribution of individual metrics, which a recommendation module translates into actionable software refactoring recommendations. [FIG. 6]
Disclaimer: Curated by HT Syndication.
