MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202541078939 A) filed by International Institute Of Information on August 20, 2025, for System And Method For Area And Power-Efficient Frequency Doubling Using Self-Biased Duty Cycle Feedback Control.
Inventors include Abhishek Srivastava; Busam Karthikeya; Vellanki Venkata Sundara Raghava Chetan Krishna; Santosh Yachareni; and Saraswatula Sree Rama Krishna Chaithnya.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: A system for area and power-efficient frequency doubling using self-biased duty cycle feedback control is provided. The system 100 includes edge processing circuitry?102, delay cell 104, and feedback circuit 106. The edge processing circuitry 102 and delay cell 104 are received input clock signal simultaneously. The delay cell 104 applies a controllable delay to the input signal to generate delayed version of input signal. The edge processing circuitry?102 receives original input signal and its delayed version as inputs and produces output signal. The feedback circuit 106 extracts DC component from output signal by duty cycle detector, amplifies DC component using self-biased inverter amplifier to generate analog voltage, converts analog voltage signal into pulsed control signal using chain of inverters, generates control voltage by filtering pulsed signal using RC filter, and feeds-back the control voltage to delay cell 104 to dynamically adjust the delay, thereby maintaining effective frequency doubling. FIG. 1
Disclaimer: Curated by HT Syndication.
