MUMBAI, India, Aug. 24 -- Intellectual Property India has published a patent application (202641098567 A) filed by Dr. Sudeshna Surabhi; Boban Mathews; Anitha. L; Dr. Shreesha Kalkoor Mudradi; Rajani; Aparna Sumant Kulkarni; and Arunkumar. A S on August 14, 2026, for System And Method For Ai-Driven Adaptive Test Pattern Generation And Fault Diagnosis In Vlsi Integrated Circuits Using Reinforcement Learning.
Inventors include Dr. Sudeshna Surabhi; Boban Mathews; Anitha. L; Dr. Shreesha Kalkoor Mudradi; Rajani; Aparna Sumant Kulkarni; and Arunkumar. A S.
The application for the patent was published on August 21, 2026, under issue no. 34/2026.
Abstract: ABSTRACT OF THE INVENTION Title: System and Method for AI-Driven Adaptive Test Pattern Generation and Fault Diagnosis in VLSI Integrated Circuits Using Reinforcement Learning The present invention provides a system and method for AI-driven adaptive test pattern generation and fault diagnosis in VLSI integrated circuits using reinforcement learning. The system comprises a circuit graph neural network encoder, an RL policy network for pattern generation, a fault simulation engine, a configurable reward function, and an integrated fault diagnosis engine. The GNN encoder learns rich circuit representations, the RL agent adaptively generates optimised test patterns, and the diagnosis engine localises faults. The system achieves higher fault coverage with fewer test patterns and reduced backtracking compared to conventional ATPG, while simultaneously providing comprehensive fault diagnosis and localisation capabilities.
Disclaimer: Curated by HT Syndication.
