MUMBAI, India, Oct. 12 -- Intellectual Property India has published a patent application (202621088299 A) filed by Persistent Systems Limited on July 20, 2026, for System And Method For A Verification-Aware Ai Execution Framework With Correlation-Aware Evidence Aggregation.
Inventors include Mr. Hritvik Shrivastava; and Ms. Rishita Sharma.
The application for the patent was published on October 09, 2026, under issue no. 41/2026.
Abstract: A verification-aware execution framework (100) treats verification of artificial-intelligence workflow outputs as a dynamically selected and economically optimized operation. An artifact (110) is segmented into verifiable units to which a defect model (120) assigns defect classes (220) and prior probabilities. A verification graph (200) associates each unit with verification nodes (210) carrying true-positive and false-positive rates, independence attributes, cost, and pass, fail, abstain, and inconclusive states. A verification scheduler (140) selects verifiers by a value that weighs defect probability, impact, and detection rate against verifier cost and false- alarm cost, runs deterministic checks first, and stops early when a calibrated quality posterior meets a risk-weighted threshold. An evidence aggregator (160) composes heterogeneous evidence while discounting correlated judges using a dependence matrix. Detected defects are routed to defect-specific repair with localized re- verification. Verifier outputs are calibrated against trusted outcomes with drift detection.
Disclaimer: Curated by HT Syndication.
