MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202647107493 A) filed by Tenstorrent Usa, Inc. on September 07, 2026, for Static Instruction Caching In A Coprocessor Architecture.
Inventor includes Dooley, Miles, Robert.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: Methods and systems relating to improved coprocessing architectures with static instruction caching are disclosed herein. A disclosed coprocessor architecture includes a processor, a coprocessor defined by an instruction set, a cache of static instruction blocks, and an instruction cache. The instruction set includes at least one static instruction. The instruction cache is configured to identify instructions in a series of instructions as either static instructions or dynamic instructions. The instruction cache is configured to, in response to identifying two or more sequential instructions in the series of instructions as static instructions, cache the two or more sequential instructions in the cache of static instruction blocks as an instruction block and store a program counter value of a program counter. The instruction cache is configured to provide the instruction block to the coprocessor from the cache of static instruction blocks when the program counter returns to the program counter value.
Disclaimer: Curated by HT Syndication.
