MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202641101328 A) filed by Sr University on August 21, 2026, for Speed And Reliability Analysis Of Single-Exact And Single/Dual Approximate Adders For Next-Generation Approximate Processors.
Inventors include Venne Srilatha; and Padala Sunitha.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: ABSTRACT The present invention relates to a configurable arithmetic architecture for speed and reliability analysis of single-exact, single-approximate, and dual-approximate adders for next-generation approximate processors. The architecture comprises operand input registers, a bit-partitioning unit, an exact adder, one or more approximate adder sections, carry-management circuitry, a mode- selection controller, output-selection circuitry, and a reliability evaluation mechanism. The proposed system selectively processes operand bits using exact or approximate arithmetic according to application requirements. In single-approximate operation, selected lower-significance bits are processed using simplified approximate logic while higher-significance bits are processed exactly. In dual- approximate operation, different approximation levels are applied to separate bit regions to provide enhanced control over accuracy and performance. The architecture enables evaluation of propagation delay, operating frequency, power consumption, hardware area, error distance, error rate, and numerical reliability. The configurable approach provides a controlled trade-off between computational speed, energy efficiency, hardware complexity, and arithmetic accuracy for approximate processors and error-tolerant applications.
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