MUMBAI, India, June 26 -- Intellectual Property India has published a patent application (202641072847 A) filed by Vellore Institute Of Technology on June 12, 2026, for Spatially Aware Defect Severity Scoring And Automated Routing For Printed Circuit Boards.
Inventors include Aju D; and Sriraam Av.
The application for the patent was published on June 19, 2026, under issue no. 25/2026.
Abstract: ABSTRACT SPATIALLY AWARE DEFECT SEVERITY SCORING AND AUTOMATED ROUTING FOR PRINTED CIRCUIT BOARDS A method for spatially aware defect severity scoring and automated factory routing in printed circuit boards comprises acquiring an image of a printed circuit board (100) by an image acquisition module (102), and processing the image by an object detection engine (104) to detect defects, outputting bounding box coordinates and a classification for each defect. A contextual severity engine (106) computes a base severity score based on a normalized defect area and a class weight. The contextual severity engine (106) computes a spatial proximity penalty by calculating Euclidean distances between defect centroids and adding a severity boost when the distance falls below a proximity threshold. The contextual severity engine (106) generates an aggregate board score based on base severity scores and spatial proximity penalties. An automated triage module (108) routes the printed circuit board (100) to a factory process based on the aggregate board score.
Disclaimer: Curated by HT Syndication.
