MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641113884 A) filed by Saveetha Engineering College on September 23, 2026, for Sparsity-Aware Mixed-Precision Reconfigurable Systolic Array For Neural Network Acceleration.
Inventor includes Sunitha T.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: The invention relates to an architecture and method for a systolic array that operates at runtime to strengthen computing of a deep neural network on a VLSI-based Al hardware accelerator. Systolic arrays based on the principle that they skip individual multiply-accumulate opefations tend to be unable to match the throughput or energy efficiency of the corresponding dense-array implementation, since the latency of a row in the array and of a column in the array is still determined by the slowest still-active processing element, and such arrays are often limited to specific sparsity patterns at the time of compression. The present invention provides solutions to such problems by providing a lookahead sparsity prediction unit to identify non-zero weight and non-zero activation operand pairs before they reach the front of the compute fabric, a reconfigurable operand-routing fabric that compactly, physically maps said nonzero operand pairs into a smaller, contiguous subset of processing elements while gating inactive elements, and a precision control unit to reconfigure each processing element's multiply-accumulate.
Disclaimer: Curated by HT Syndication.
