MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641109518 A) filed by Indian Institute Of Technology Madras Iit Madras on September 11, 2026, for Sparse Operand Matching Unit For A Neural Network Accelerator.
Inventors include Srinivasan, Gopalakrishnan; Bawa Venkatesh, Devgokul; and Radhakrishnan, Sreeram.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: ABSTRACT SPARSE OPERAND MATCHING UNIT FOR A NEURAL NETWORK ACCELERATOR A sparse operand matching unit for a neural network accelerator including a bitmask combiner, an index generator, a first offset generator, a second 5 offset generator and an output interface. The bitmask combiner to combine an activation bitmask and a weight bitmask to obtain a match result. The index generator coupled to the bitmask combiner and is to output one matched index per clock cycle from the match result. The first offset generator is to compute an activation offset into the compressed activation 10 data structure by counting non-zero positions preceding the matched index within the activation bitmask for each matched index. The first offset generator having a first processing latency of a plurality of clock cycles. The second offset generator coupled to the index generator and is to compute a weight offset into the compressed weight data structure by counting non- 15 zero positions preceding the matched index within the weight bitmask for each matched index. The second offset generator having a second processing latency equal to the first processing latency. The output interface is to forward the activation offset and the weight offset to an accumulation stage. 20 Fig. 1 58
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