MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202641065627 A) filed by Nandha Engineering College on May 25, 2026, for Sparse Kogge Stone Adder Based Approximate Multiplier For Efficient Image Processing.
Inventors include R. Murugasami; and A. Manoj.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: ABSTRACTOrTHEIN VENTION Image processing applications demand high-speed and power-efficient multipliers capable of tolerating minor arithmetic inaccuracies without degrading perceptual quality. Conventional designs typically employ adders such as the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), or Carry Select Adder (CSLA) for final partial product accumulation. However, these adders exhibit increased delay, area overhead, and limited fault resilience, especially in large bit-width and error- prone environments. To address these limitations, this work proposes an approximate multiplier architecture that integrates a fault- tolerant Sparse Kogge-Stone Adder (SKSA) at the final accumulation stage. The SKSA enables fast and area- efficient carry propagation while incorporating redundancy mechanisms for fault detection and correction. Approximate addition is selectively applied at the lower significant bits (LSBs) to further optimize power and hardware complexity, while maintaining acceptable accuracy for image enhancement operations. The proposed architecture generates partial products using approximate logic and accumulates them through the SKSA, Implementation and verification are carried out in Verilog HDL using the Xilinx Vivado tool on an Artix-7 FPGA platform. Experimental results demonstrate that the proposed design achieves reduced power consumption, shorter propagation delay, and reduced area compared to RCA-, CSA-, COSA-, and CSLA-based designs, making it highly suitable for real-time, error-tolerant image processing systems.
Disclaimer: Curated by HT Syndication.
