MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641110059 A) filed by Vellore Institute Of Technology on September 14, 2026, for Six-Transistor Sram Cell Using Junctionless Gate-All-Around Nanowire Field-Effect Transistors.
Inventors include Nawaz Shafi; Siddhant Pandey; Roumak Saha; and Mediboyina Taniskha.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: ABSTRACT SIX-TRANSISTOR SRAM CELL USING JUNCTIONLESS GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS A six-transistor (6T) static random-access memory (SRAM) cell includes six junctionless gate-all-around nanowire field-effect transistors (FETs). Each junctionless gate-all-around nanowire FET includes a cylindrical silicon nanowire body having a source region (2), a channel region (5), and a drain region (7) arranged along an axial direction of the nanowire body. The source region (2), the channel region (5), and the drain region (7) have a same conductivity type and a same dopant concentration such that no metallurgical junction exists therebetween. A gate dielectric layer (4) conformally surrounds an outer circumference of the channel region (5). A gate electrode (3) is disposed on the gate dielectric layer (4) and circumferentially surrounds the channel region (5) to form a gate-all-around structure. A source contact (1) is electrically coupled to the source region (2), and a drain contact (8) is electrically coupled to the drain region (7). The six junctionless gate-all-around nanowire FETs are interconnected as a cross-coupled inverter pair with two access transistors to store one bit of data.
Disclaimer: Curated by HT Syndication.
