MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202611110309 A) filed by Chandigarh University on September 14, 2026, for Silicon-Accelerated Probabilistic Inference Co-Processor For Real-Time Bayesian Uncertainty Quantification.
Inventors include Shaman Sharma; Manoj Gaur; and Deepak Kumar.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: A silicon-implemented probabilistic inference co-processor is provided for real-time Bayesian uncertainty quantification associated with machine-learning inference outputs. The co-processor includes a high-speed interface controller (202), a probabilistic compute core array (203), a stochastic number generation module (204), a distribution processing unit (205), a probabilistic memory unit (206), a Bayesian inference engine (207), and a decision and safety interface (208). Prediction information received from a host processor (201) is represented as probability distributions and processed using hardware-generated random values and distribution- level arithmetic. Prior and likelihood information are combined to generate posterior distributions, from which uncertainty and confidence information are produced and returned to the host processor. A threshold-based safety indication may be generated when uncertainty exceeds a defined condition. The architecture provides dedicated hardware for parallel probabilistic processing in edge and autonomous systems.
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