MUMBAI, India, Oct. 26 -- Intellectual Property India has published a patent application (202641123902 A) filed by Srm Institute Of Science And Technology, Ramapuram; and Easwari Engineering College on October 16, 2026, for Self Adaptive Clocking System For Low Power Vlsi Design.
Inventors include Dr. N. Mahesh Kumar; Santo Briana A; Aishwarya R; Pavatharani V; and Sraddha Jothi Manikandan.
The application for the patent was published on October 23, 2026, under issue no. 43/2026.
Abstract: Abstract In synchronous digital circuits, fixed frequency clocking wastes dynamic power when activity is low. This is a serious issue for battery-powered embedded systems, IoT devices and applications with varying computational workloads . The present invention discloses a Self-Adaptive Clocking System that continuously monitors a two-bit workload activity indicator and automatically selects one of three pre-generated clock frequencies: full speed, half speed, or quarter speed, generated from a single master oscillator. The system is implemented in four modular Verilog HDL submodules: Clock Divider, Activity Controller, Adaptive Multiplexer and Top Module, each independently verifiable and extensible. The design correctness was demonstrated through behavioural simulation in Xilinx ISE and physical implementation on a Tang Nano 9K FPGA board using Gowin EDA toolchain, to demonstrate real-time adaptive behaviour in the form of visually observable changes in LED blink rates. For a representative mixed workload, with 60% of the runtime in low-activity conditions, the system delivers 45% dynamic power savings compared to a fixed frequency baseline with negligible logic overhead (three flip-flops, four look-up tables, and two I/O buffers) and no loss in peak throughput.
Disclaimer: Curated by HT Syndication.
