MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202617096923 A) filed by Thales Dis France Sas on August 11, 2026, for Secure Non-Volatile Memory.
Inventors include Naura, David; and Bour, Laureline.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: The invention relates to a non-volatile memory circuit (300) having an attack detector (390) comprising a supplemental bit line (BL') carrying supplemental memory cells (MC') located at the intersection with each word line (WLj). A supplemental polarization circuit (369) polarizes the supplemental bit line (BL'). The supplemental polarization circuit (369) provides a detection current higher than the current drawn by one supplemental memory cell (WC'), and lower than the current drawn by at least two memory cells (WC'). A supplemental reading amplifier (379) connected to the supplemental bit line (BL') can read a first state when one supplemental memory cell (WC') is selected by one word line (WLj) and can read a second state when two or more supplemental memory cells (WC') are simultaneously selected by at least two word lines (WLj). The supplemental reading amplifier (379) providing an alarm signal (ALARM) when the reading corresponds to the second state.
Disclaimer: Curated by HT Syndication.
