MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202617075623 A) filed by Thales Dis France Sas on June 18, 2026, for Secure Non-Volatile Memory.
Inventors include Naura, David; and Bour, Laureline.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: The invention relates to a non-volatile memory circuit (300) comprising a plurality of memory cells (MCj,i), a plurality of bit lines (BLi) and a plurality of word lines (WLj to WLj+2), each memory cell (MCj,i) comprising a floating gate transistor (Tfg) for memorizing a bit value and being located at the intersection of a bit line (BLi) and of a word line (WLj), said non-volatile memory circuit (300) comprising a polarization circuit (360) for polarizing the bit lines (BLi) with a constant current, and reading amplifiers (370) connected to bit lines (BLi) for reading the value of memory cells (MCj,i) selected by one of the word lines (WLj). The memory circuit (300) further comprises an attack detector (390) comprising at least one detection circuit (391) having a first input terminal connected to at least one bit line (BLi) for detecting an abnormal voltage on the bit line (BLi) and for providing an alarm signal (ALARM) on an output terminal when the abnormal voltage is detected.
Disclaimer: Curated by HT Syndication.
