MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641108830 A) filed by Vellore Institute Of Technology, Chennai on September 10, 2026, for Secure Multi-Factor Attendance Verification System.
Inventors include K. P. Vijayakumar; K. Pradeep; Sushindh Anandan; Shaik Mohammed Arif; P Hari Krishna Reddy; and Vinjanampati Naga Sairama Srikar.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: The present disclosure relates to a system (102) and method (400) for secure multi-factor attendance verification. The system (102) comprises a processor (202) and memory (204) generating a time-sliced machine-readable token comprising a signed payload including a session identifier, time-slice index, time-to-live parameter, and nonce, with a synchronized numeric challenge derived from the same payload. A participant device (108) scans the token, submits the matching numeric challenge, and the system (102) validates the cryptographic signature, time-to-live parameter, and nonce. Upon successful validation, the system (102) issues a short-lived scan ticket gating biometric liveness detection and facial authentication by the participant device (108), with attendance recorded in the database (210) only upon successful completion of verification, providing multi-layered, hardware-agnostic protection against proxy fraud, replay attacks, and biometric spoofing.
Disclaimer: Curated by HT Syndication.
