MUMBAI, India, Oct. 26 -- Intellectual Property India has published a patent application (202642051343 A) filed by Centre Of Excellence In Wireless Technology Iit Madras; and Indian Institute Of Technology Madras Iit Madras on April 22, 2026, for Scheduling Synchronization Signal And Control Resource Set Zero (coreset#0) Resources.
Inventors include Deepak Agarwal; Deepak Padmanabhan Mayakumar; Thirunageswaram Ramachandran Ramya; Sheetal Kalyani; Jeniston Deviraj Klutto Milleth; and Bhaskar Ramamurthi.
The application for the patent was published on October 23, 2026, under issue no. 43/2026.
Abstract: ABSTRACT “SCHEDULING SYNCHRONIZATION SIGNAL AND CONTROL RESOURCE SET ZERO (CORESET#0) RESOURCES” The present invention discloses a method and a first node (300) for scheduling at least one synchronization signal (SS) and control resource set zero (CORESET#0) resources of the first node (300). The method includes selecting, by the first node (300), a non-overlap strategy for the at least one SS and at least one candidate CORESET#0 slot, generating, by the first node (300), one of an updated schedule and a table entry for the CORESET#0 resources according to the non-overlap strategy and transmitting, by the first node (300), at least one of a control information and the at least one SS based on one of the updated schedule and the table entry. FIG. 10
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