MUMBAI, India, June 26 -- Intellectual Property India has published a patent application (202641073547 A) filed by Mlr Institute Of Technology on June 13, 2026, for Risc-V Processor Suitable For Implementation On Fpga And Asic Platforms.

Inventors include Mr. Haribabu Yadav Kolusu; Ms. G. Sravani; Mr. G. Abhinaya Goud; and Mr. J. Adithya.

The application for the patent was published on June 19, 2026, under issue no. 25/2026.

Abstract: The present invention relates to the design and implementation of a 32-bit pipelined processor based on the open-standard RV32I Version 2.0 instruction set architecture of RISC-V. The processor adopts a Reduced Instruction Set Computer (RISC) architecture, enabling simplified instruction execution and reduced hardware complexity compared to conventional Complex Instruction Set Computer (CISC) systems. The processor is structured using a five-stage pipelined architecture comprising instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM), and write-back (WB) stages, thereby improving overall system performance through parallel instruction processing. The architecture includes key functional modules such as pipeline registers, arithmetic logic unit (ALU), ALU decoder, main control unit, instruction memory, data memory, register file, program counter (PC) multiplexer, and result multiplexer, all interconnected to form an efficient data path. Dedicated pipeline registers are employed between stages to ensure proper synchronization and data transfer. A hazard detection and mitigation unit is incorporated to handle data and control hazards, thereby maintaining correct execution flow and improving reliability. The processor design is described using Verilog Hardware Description Language and verified through simulation using standard design tools. The open and extensible nature of the RISC-V instruction set architecture enables flexible hardware and software development, making the processor suitable for scalable and customizable embedded system applications. The invention provides an efficient, modular, and high-performance pipelined processor architecture suitable for FPGA and ASIC implementations.

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