MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641107754 A) filed by Dr. K. Karthik; and Priyadarsini K on September 08, 2026, for Reconfigurable Hardware Accelerator For Cardiac Arrhythmia Detection Using Fused Morphological And Temporal Features.
Inventors include Dr. K. Karthik; and Priyadarsini K.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: Title: Reconfigurable Hardware Accelerator for Cardiac Arrhythmia Detection Using Fused Morphological and Temporal Features A reconfigurable hardware accelerator and cardiac monitoring system for beat-level arrhythmia detection are disclosed. The accelerator processes digitised electrocardiogram beats using convolution engines (50), a reduction engine (60), a concatenation buffer (70), a fully-connected engine (80) and a comparison engine (90). The convolution engines (50) employ synchronous activation and coefficient memory access, wherein addresses for a current operation are generated before product formation and addresses for a succeeding operation are concurrently driven, permitting coefficient storage in dedicated block memory of a reconfigurable device. Morphological features generated from the ECG beat are concatenated with quantised inter-beat timing features in a common fixed-point representation and processed by a single fully-connected engine. Independently parameterised arithmetic scaling is applied at different processing stages to accommodate different coefficient magnitudes while retaining precision under reduced-width fixed-point representation. The accelerator may be time-multiplexed among multiple monitored positions, with classification results mapped to graded escalation levels for display./td /tr /t
Disclaimer: Curated by HT Syndication.
