MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641079715 A) filed by Sona College Of Technology on June 29, 2026, for Real-Time Continuous Invisible Watermarking System Using Fpga-Based Pipelined Image Processing.
Inventors include Saranya K; Vijayashaarathi S; Karuniyaa S; Rubitha S; Vijipriya M; Sasirekha N; Harirajkumar J; and Vivek Karthick P.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: ABSTRACT An FPGA-based invisible watermarking system (100) and method are disclosed, utilizing a transform-domain sequential architecture for enhanced robustness and deterministic processing. The system comprises an image acquisition and normalization module (105), a 2D-Discrete Wavelet Transform (DWT) engine (110), a watermark injection subsystem (120, 125, 128, 130), a 2D- Inverse DWT (IDWT) engine (140), and an output frame buffer (150). Host image pixels (102) of $128 imes 128$ resolution are decomposed by the 2D-DWT engine (110) into frequency sub-bands, including an LL (Approximation) sub-band (112) and detail sub- bands (113, 114, 115). A watermark embedder (130), controlled by a user interface layer (170) for strength adjustment (172), modifies the LL sub-band coefficients to incorporate invisible $64 imes 64$ watermark data while maintaining a high peak signal-to-noise ratio (PSNR). The system utilizes a sequential finite state machine hardware architecture that processes one complete image through all stages before accepting the next, ensuring a deterministic latency of approximately 0.5 milliseconds per image. This architecture provides fixed-point arithmetic implementation and improved resistance to spatial attacks such as cropping and compression, making it suitable for secure document authentication, medical imaging, and copyright protection of static digital images.
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