MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202631097819 A) filed by National Institute Of Technology Rourkela Nit Rourkela on August 13, 2026, for Radiation-Hardened Digital Logic Cell And Method For Suppressing Radiation-Induced Transient Upsets.
Inventor includes Sarkar, Santanu.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: The present invention relates to a radiation-hardened digital logic cell (100) and a method (200) for suppressing radiation-induced transient upsets in a digital circuit. The digital logic cell (100) comprises a NAND gate (108), a first transistor network (104), a third transistor (106), a second transistor network (110), and an output inverter (112). The first transistor network (104) and the second transistor network (110) cooperatively provide complementary charge dissipation and charge restoration paths to automatically restore an intended logic state at a Node X following a radiation-induced transient without disturbing normal logic operation or employing redundancy circuitry. The method (200) comprises receiving a common input signal, generating an output at the Node X, controlling charge through the first and second transistor networks, and restoring the intended logic state. The present invention is applicable to radiation-hardened digital circuits for aerospace, defence, and other radiation-prone electronic systems.
Disclaimer: Curated by HT Syndication.
