MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202621081958 A) filed by Teqsil Labs Private Limited on July 02, 2026, for Processor Architecture With Metadata-Driven Hardware Enforcement For Concurrent Control Of Memory Access Operations.
Inventors include Ms. Trushna Nishant Kasture; and Mr. Nishant Dinkarrao Kasture.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: ABSTRACT PROCESSOR ARCHITECTURE WITH METADATA-DRIVEN HARDWARE ENFORCEMENT FOR CONCURRENT CONTROL OF MEMORY ACCESS OPERATIONS A processor (102) for performing metadata-driven control of memory access operations is disclosed. The processor (102) comprises a register file (104) including a plurality of general-purpose registers, each register comprising a data portion (106) and a structured architectural metadata portion (108) including a plurality of metadata sub-fields associated with respective hardware control attributes. A load-store execution unit (110) performs a memory access operation using a source-address register received from the register file (104). A central hardware enforcement unit (112) receives the structured architectural metadata portion (108) associated with the source-address register, simultaneously evaluates the plurality of metadata sub-fields, generates corresponding hardware control outputs, and communicates the hardware control outputs to one or more hardware modules associated with execution of the memory access operation. FIG. 1 will be the reference figure.
Disclaimer: Curated by HT Syndication.
