MUMBAI, India, Aug. 17 -- Intellectual Property India has published a patent application (202617079978 A) filed by Wolfspeed, Inc. on June 29, 2026, for Power Semiconductor Device Having Improved Transient Handling Without Field Insulating Layer.
Inventors include Van Brunt, Edward, Robert; Barkley, Adam, Benjamin; Ji, In-Hwan; and Harrington, Iii, Thomas, Edgar.
The application for the patent was published on August 14, 2026, under issue no. 33/2026.
Abstract: Power semiconductor devices are provided. In one example, a power semiconductor device includes a semiconductor structure. The power semiconductor device further includes a polysilicon gate layer on the semiconductor structure in an inactive region of the semiconductor device. The power semiconductor device further includes a gate insulating pattern between the polysilicon gate layer and the semiconductor structure, the gate insulating pattern having a thickness such that a distance between the semiconductor in the inactive region and the polysilicon gate layer through the gate insulating pattern is less than about 100 nm. The power semiconductor device further includes a shunt contact structure on semiconductor structure in the inactive region. A gate insulating electric field across the gate insulating pattern associated with a displacement current is less than about 8 MV/cm.
Disclaimer: Curated by HT Syndication.
