MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115554 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for Power-Efficient Yolo V3 Accelerator Using Booth And Wallace Arithmetic Units.
Inventor includes Dr. V. Priyanka Brahmaiah.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0025] Deep learning models like YOLO v3 excel at real-time object detection but demand significant power, limiting their use on resource-constrained devices. This project tackles this limitation by introducing a power-efficient modification to the YOLO v3 architecture. The key innovation involves replacing standard arithmetic units with Booth multipliers and Wallace tree adders directly within the network's computational structure. Booth multipliers inherently reduce partial products during multiplication, a crucial operation in YOLO v3's convolutional layers, leading to lower power consumption and simpler hardware. Simultaneously, Wallace tree adders accelerate the summation of these partial products through their parallel nature and carry-save methodology, minimizing delays and enabling operation at lower voltages for further power savings. Experimental results highlight the effectiveness of this approach, demonstrating a substantial 75-85% reduction in power consumption without impacting the object detection capabilities or accuracy of the original YOLO v3 model. This significant improvement unlocks the potential for deploying computationally intensive deep learning models on energy-limited devices, opening doors for real-time applications in various practical settings.
Disclaimer: Curated by HT Syndication.
