Intellectual Property India Publishes Patent Application for Post-Processing Safety Validation System And Method For Deterministic Sensor-Authority Governance With Persistent Trust Modulation, Cryptographic Telemetry Authentication, And Hardware-Level Resource Isolation On Mobile Computing Devices

MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202611074263 A) filed by Saksham Chawla on June 15, 2026, for Post-Processing Safety Validation System And Method For Deterministic Sensor-Authority Governance With Persistent Trust Modulation, Cryptographic Telemetry Authentication, And Hardware-Level Resource Isolation On Mobile Computing Devices.

Inventor includes Saksham Chawla.

The application for the patent was published on July 31, 2026, under issue no. 31/2026.

Abstract: A post-processing safety validation system and method executing on a mobile computing device enforces deterministic, hardware-anchored governance of risk signals generated by an AI inference pipeline. A validation controller thread is affinity-pinned to a dedicated physical CPU core via a direct OS core-assignment system call, isolating it from scheduler interference affecting the primary inference pipeline. IMU telemetry is acquired via a synchronous hardware interrupt binding to the IMU sensor Hardware Abstraction Layer and cryptographically authenticated against a hardware-fused keystore. A comparator logic module computes divergence between the risk signal and authenticated IMU telemetry and produces a binary validation output. A non-volatile authority register persisted to a NAND flash block-locked hardware partition is asymmetrically decremented on validation failure and incremented on validation pass, with the updated state surviving application restart and device reboot. An output governor scales the risk signal in proportion to the authority value. In advanced embodiments, the system further comprises thermal-adaptive ISP resolution governance based on hardware thermistor data, ARM TrustZone Secure World isolation, and pre-computed look-up table normalisation for heterogeneous sensor data. The system enforces deterministic timing on non-deterministic mobile hardware, improves NAND flash memory longevity, and provides hardware-anchored exploitation resistance compliant with the technical effect requirements of Section 3(k) of the Patents Act, 1970.

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