MUMBAI, India, Aug. 24 -- Intellectual Property India has published a patent application (202641098531 A) filed by Budati Anil Kumar; Gowthamigudisa; Vijay Rao Kumbhare; and Aditya Japa on August 14, 2026, for Performance-Optimized Hybrid Vgsot–mtj/Cmos Logic-In-Memory Circuits With Vcma-Enhanced Switching.
Inventors include Gowthamigudisa; Vijay Rao Kumbhare; Aditya Japa; and Budati Anil Kumar.
The application for the patent was published on August 21, 2026, under issue no. 34/2026.
Abstract: Logic–In–memory (LIM) is a key methodology to address energy–efficient, high–speed computing challenges. The voltage–gated spin–orbit torque magnetic tunnel junction (VGSOT–MTJ) has emerged as a leading solution, offering low energy consumption and reduced delay. This study leverages VGSOT–MTJ's characteristics to advance LIM architectures, focusing on performance evaluation. The results show significant improvements in power dissipation, delay, and energy, demonstrating the device's potential for energy–efficient circuit/logic design. Notably, the proposed hybrid design exhibits a 36.1% and 16.21% improvement in worst–case delay compared to previous XOR/XNOR designs. Similarly, a 23.71% and 17.04% enhancement are observed for AND/NAND logic, while the hybrid OR/NOR logic demonstrates a 20.51% and 35.445% improvement in worst–case delay. The full adder logic also outperforms previous designs and achieves a 9.6% lower worst–case delay. These findings demonstrate that the presented hybrid VGSOT–MTJ/CMOS LIM–based logic designs enable energy–efficient systems through integrated computation. Such capabilities are particularly relevant for resource–constrained systems, such as IoT nodes, edge devices, and embedded platforms, that are increasingly deployed in everyday life, where high–speed and energy efficiency are essential.
Disclaimer: Curated by HT Syndication.
