Intellectual Property India Publishes Patent Application for Package Comprising Integrated Devices And Bridge Coupling Top Sides Of Integrated Devices

MUMBAI, India, Sept. 7 -- Intellectual Property India has published a patent application (202648102462 A) filed by Qualcomm Incorporated on August 25, 2026, for Package Comprising Integrated Devices And Bridge Coupling Top Sides Of Integrated Devices.

Inventors include Chava, Bharani; Roy, Abinash; Song, Stanley Seungchul; and Kim, Jonghae.

The application for the patent was published on September 04, 2026, under issue no. 36/2026.

Abstract: ABSTRACT PACKAGE COMPRISING INTEGRATED DEVICES AND BRIDGE COUPLING TOP SIDES OF INTEGRATED DEVICES A package comprising: a first substrate comprising at least one dielectric layer; a first integrated device coupled to the first substrate through at least a first plurality of pillar interconnects and a first plurality of solder interconnects; a second integrated device coupled to the first substrate through at least a second plurality of pillar interconnects and a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects, wherein the second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device, wherein the second bridge comprises: a silicon substrate comprising silicon; a plurality of bridge interconnects; a passivation layer coupled to the silicon substrate, wherein the passivation layer is a different material from the at least one dielectric layer of the first substrate; wherein the fourth plurality of solder interconnects directly touches the plurality of bridge interconnects of the second bridge, wherein the second bridge is embedded in the first substrate such that there is no dielectric layer from the first substrate that is located vertically between the passivation layer of the second bridge and the first integrated device, and wherein a side portion of the passivation layer of the second bridge touches the first substrate.

Disclaimer: Curated by HT Syndication.