MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641076302 A) filed by Pokkunuri Pardha Saradhi; Sadhu Satya Sravani; B. Balaji; and Koneru Lakshmaiah Education Foundation on June 19, 2026, for On Current Analysis Of Halo Doped Hetero Dielectric Gate Oxide Double Gate Tunnel Field Effect Transistor With Spacers.
Inventors include Sadhu Satya Sravani; B. Balaji; and P. Pardhasaradhi.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: This evaluation explores on techniques for enhancing device parameters of Double Gate Tunnel Field Effect Transistor structure such as drain current and ratio of ON current to OFF current (ION / IOFF). The Conventional Double Gate Tunnel Field Effect Transistor (DGTFET) suffers from the limitation of ON current. A novel state of art of TFET i.e., Halo doped Hetero dielectric gate oxide Double Gate TFET with spacers (HH-DGTFETS) is introduced in this work. High-k material spacer technique and dielectric gate oxide engineering can help in increasing the drain current and lower the leakage current providing higher ON to OFF current ratio. The Structure is being modeled and parameters of the structure are analyzed using TCAD Silvaco Atlas software tool. The analysis results in the amount of ON Current of 1.1648A/µm and the ratio of ON current to OFF current of 8.6×1011. Therefore the structure proposed can be used in low power applications.
Disclaimer: Curated by HT Syndication.
