MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641109519 A) filed by Indian Institute Of Technology Madras Iit Madras on September 11, 2026, for On-Chip Processing Neural Network Accelerator.
Inventors include Srinivasan, Gopalakrishnan; Bawa Venkatesh, Devgokul; and Radhakrishnan, Sreeram.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: ABSTRACT 5 ON-CHIP PROCESSING NEURAL NETWORK ACCELERATOR An on-chip processing neural network accelerator includes an on-chip input buffer and an on-chip sparse operation generation engine. The on-chip input buffer receives dense activation data from an off-chip memory. The dense activation data is the data received from previous layer of neural network or 10 an input feature map supplied to an input layer of the neural network. The on-chip sparse operation generation engine is to perform a matrix reorganization operation on the dense activation data to rearrange the dense activation data into a transformed format for computational operations on a plurality of processing units. The computational operation 15 comprises at least one of a convolution operation or a matrix multiplication operation. The on-chip processing neural network accelerator generates a compressed sparse representation from the transformed format. The compressed sparse representation includes a position indicator and a compressed data array. The position indicator to identify locations of non- 20 zero elements within the transformed format. The compressed data array to include values of non-zero elements. Fig. 2 49
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