MUMBAI, India, Oct. 26 -- Intellectual Property India has published a patent application (202644040850 A) filed by Google LLC on March 31, 2026, for Non-Scannable Flip-Flop For A Scannable Digital Circuit.
Inventors include Arimilli, Rajesh; and Saifee, Shabbir.
The application for the patent was published on October 23, 2026, under issue no. 43/2026.
Abstract: ABSTRACT Implementations described herein relate to non-scannable flip-flops used within scannable digital circuits. For example, an illustrative method includes determining that a first propagation delay of a first stage of combinatorial logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design, and, based on that determination, modifying the scannable digital circuit design to integrate a multiplexing function controlled by a scan enable signal into the first stage and to convert the first scannable flip-flop into a non-scannable flip-flop. The method further includes determining that a second propagation delay of a second stage of combinatorial logic is less than the delay threshold, the second stage preceding a second scannable flip-flop within the scannable digital circuit design, and, based on that determination, retaining the second scannable flip-flop in the circuit design. Corresponding methods, circuits, media, and other implementations are also disclosed.
Disclaimer: Curated by HT Syndication.
