MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202541000645 A) filed by Hindusthan Institute Of Technology on January 03, 2025, for Modifying The Parallel Prefix Adder By Implementing A Low Power Hybrid Full Adder.
Inventors include Dr. C. Natarajan; Mr. A. Abdul Hayum; Dr. B. Paulchamy; Ms. N. Rambrabha; Mr. A. Vidhyaseka R; Mrs. L. Yogapriya; and Dr. J. Ramya.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: 7. ABSTRACT OF THE INVENTION: Parallel Prefix Adders (PPAs) are crucial in high-performance computing and digital signal processing due to their efficiency in performing fast arithmetic operations. This paper focuses on enhancing the PPA's performance by integrating a novel low-power hybrid full adder design. The proposed hybrid full adder leverages a combination of transmission gates, XOR-XNOR gates, and CMOS logic to achieve significant reductions in power consumption and area while maintaining high-speed operation. The modified PPA architecture is analyzed for its power, delay, and energy efficiency across various supply voltages and process variations. Simulation results demonstrate that the enhanced PPA design outperforms conventional adders in terms of power- delay product (PDP), making it an ideal candidate for energy-efficient applications in modern VLSI systems. This innovation addresses the growing demand for low-power, high-speed arithmetic units in portable and embedded devices.
Disclaimer: Curated by HT Syndication.
