MUMBAI, India, June 26 -- Intellectual Property India has published a patent application (202441098540 A) filed by M. S. Ramaiah University Of Applied Sciences on December 13, 2024, for Micro Ring Resonator (mrr) Based Photonic Configurable Logic Block (pclb) And Method Thereof.
Inventors include Ugra Mohan Roy; Divya Kiran; Malathi S; Swetha K; Sneha U S; and Akshay S.
The application for the patent was published on June 19, 2026, under issue no. 25/2026.
Abstract: Micro Ring Resonator (MRR) based Photonic Configurable Logic Block (PCLB) and Method thereof A Micro Ring Resonator (MRR) based Photonic Configurable Logic Block (PCLB) (100) and method thereof is disclosed. The block (100) includes optical look up table (LUT) (102), an optical D-flip flop (104), and an optical 2X1 multipliers (106). The optical LUT (102) includes at least two 4X1 multiplexers and 2X1 multipliers with plurality of waveguides (I0-I7), one or more input lines (S0, S1, and S2), and one output waveguide (Y). The plurality of waveguides (I0-I7) are configured as input lines (A-C). The optical D-flip flop is configured with a clock signal (CLOCK). The clock signal modulates a light for allowing a data input wavelength to pass through and be stored in the MRR or a delay line. The optical 2X1 multipliers is configured as an output of the MRR based PCLB. A light representing binary values of A, B, and C is injected into the optical LUT.
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