MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641075864 A) filed by Vellore Institute Of Technology on June 19, 2026, for Method For Spatial Variability Analysis Of Electrical Parameters In Hetero-Dielectric Double-Gate Tunnel Field-Effect Transistors.
Inventors include Shanidul Hoque; Riddhi Dutta; and Aryan Bose.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: A computer-implemented method (100) for spatial variability analysis of electrical parameters in a hetero-dielectric double-gate tunnel field-effect transistor is disclosed. The method comprises generating a semiconductor device model through a structural modelling module (102), performing physics-based simulation through a simulation module (104), and calibrating the device model through a model calibration module (106). One or more interface-trap profiles are defined through a trap profile specification module (108), and interface traps are spatially localized within selected oxide-semiconductor interface segments through a spatial localization module (112). Multiple statistically randomized simulation instances are executed through an iterative simulation module (122), and electrical parameters are extracted through a parameter extraction module (124). Statistical variability metrics are determined through a statistical sensitivity mapping module (132), followed by reliability assessment through a reliability assessment module (134). The method enables localized evaluation of interface-trap-induced electrical parameter variability in semiconductor device models.
Disclaimer: Curated by HT Syndication.
