MUMBAI, India, Aug. 17 -- Intellectual Property India has published a patent application (202641096862 A) filed by Vellore Institute Of Technology on August 11, 2026, for Method For Reducing Quantum Circuit Depth Through Adaptive Gate Sequence Reordering.
Inventors include Santhi Krishnan; and Divy Kumar Agrawal.
The application for the patent was published on August 14, 2026, under issue no. 33/2026.
Abstract: ABSTRACT METHOD FOR REDUCING QUANTUM CIRCUIT DEPTH THROUGH ADAPTIVE GATE SEQUENCE REORDERING A method for reducing a depth of a quantum circuit comprises receiving, at a circuit ingestion interface (102), a quantum circuit description expressed in a gate-level intermediate representation and parsing the quantum circuit description into a directed dependency graph. A commutation evaluation unit (104) identifies candidate gate pairs satisfying a commutation relation. A telemetry acquisition subsystem (114) coupled to quantum control electronics (112) continuously samples calibration telemetry comprising native gate durations and crosstalk coupling coefficients. A gate sequence reordering engine (106) implemented in dedicated scheduling hardware computes, for each candidate gate pair, a physical pulse-sequence duration for each of two possible orderings and retains the ordering having the lower duration. The computing and retaining iterates until no further reduction is achieved, producing a reordered instruction sequence transmitted directly to a hardware pulse sequencer (108) that generates control waveforms for execution on a quantum processing unit (110).
Disclaimer: Curated by HT Syndication.
