MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202527128092 A) filed by Inova Semiconductors Gmbh on December 17, 2025, for Method And System For Calculating Forward Error Correction With A Reduced Number Of Gates In Fec Encoders.

Inventors include Kluge, Fabian; and Neumann, Roland.

The application for the patent was published on October 02, 2026, under issue no. 40/2026.

Abstract: The present invention relates to a method for improving forward error correction in serial coding during data transmission in a vehicle and, compared to the prior art, it offers, among other things, the advantage that the physical behaviour on a transmission channel can always be deterministically controlled despite a reduction in resource requirements. The proposed method reduces the number of gates in the forward error correction encoders by using the preliminary calculation of the forward error correction on individual subwords to minimise the exponential growth in the number of gates required compared to the prior art. Thus, according to the proposed method, bit errors are minimal and a transmission error can be corrected efficiently, i.e. with minimal technical effort. Furthermore, the encoders used are designed with a minimal number of gates, and the proposed method implicitly includes a form of nesting that allows so-called burst errors to be corrected particularly advantageously. This implicit nesting makes it possible to eliminate the need for the conventional buffer memories required by explicit nesting. In addition, the invention ensures that user data, together with corrective metadata, can be encoded in a manner that is advantageous for transmission. According to the invention, it can be ensured that not only the user data is line-coded or channel-coded, but also the correction data. The present invention also relates to a similarly designed system arrangement for carrying out the method, and to a computer program product comprising control commands which execute the method.

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