MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202647112275 A) filed by Ciena Corporation on September 18, 2026, for Managing Stress In Semiconductor Chips.
Inventors include Ct, Jean-Sbastien; and Blanger, Vincent.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: A first chip comprises a first set of one or more metal layers having a first thickness and comprising at least one metal layer that has a first CTE. A first volume of the first chip is adjacent to the first set of one or more metal layers. A second volume of the first chip comprises one or more electronic or photonic structures, and a second set of one or more metal layers that has a second thickness. At least one metal layer in the second set has a second CTE. A set of one or more metal structures of the first chip is adjacent to the second volume and comprises at least one metal structure electrically connected to at least a portion of at least one metal layer in the second set of one or more metal layers.
Disclaimer: Curated by HT Syndication.
