MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202611072630 A) filed by Delhi Technological University on June 11, 2026, for Low-Power Radiation-Hardened And Half-Select Immune 14t Sram Cell Architecture And Method Thereof.
Inventors include Jain, Snigdha; and Pandey, Neeta.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: The present disclosure relates to a dual-performance silicon FET-based 14-transistor (14T) static random-access memory (SRAM) cell architecture (100) configured to provide simultaneous radiation robustness and half-select disturbance immunity. The SRAM cell (100) comprises a memory cell (102) formed by cross-coupled inverter pairs (P1, N1, P2, N2), a power-gating network (104) for leakage reduction and write enhancement, a radiation-recovery circuitry (106) for restoring data after single- event and multiple-node upsets, a write-access and half-select protection circuitry (108) for controlled write operations, a decoupled read circuitry (110) for non- destructive read access via read bitline (RBL) and read wordline (RWL), and a control circuitry (112) for coordinated operation. The architecture reduces transistor count compared to conventional designs, achieving lower area, reduced power consumption, and improved performance. The integrated design ensures data integrity under radiation and prevents half-select disturbances, making it suitable for high-reliability applications such as aerospace, defense, and advanced computing systems.
Disclaimer: Curated by HT Syndication.
