MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641074847 A) filed by Mlr Institute Of Technology on June 17, 2026, for Low-Power High-Performance Ai Accelerator Using Parallel Multiply-Accumulate (mac) Array Architecture.
Inventors include Mrs. K. Mary; Mr. P. Rajesh; Ms. Aishwarya; and Ms. T. Sirisha.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: The present invention relates to a low-power and high-performance AI accelerator based on a parallel Multiply-Accumulate (MAC) array architecture. The system is designed to efficiently perform computation-intensive operations such as matrix multiplication and convolution used in artificial intelligence applications. By employing multiple MAC units operating in parallel, the invention significantly improves computational throughput and reduces processing latency. The design incorporates low-power techniques, including clock gating and precision scaling, to enhance energy efficiency. Implemented using Verilog HDL and a complete VLSI design flow, the proposed accelerator achieves an optimal balance between performance, power consumption, and hardware utilization, making it suitable for real-time, embedded, and edge AI applications.
Disclaimer: Curated by HT Syndication.
