MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641111377 A) filed by Srm Institute Of Science And Technology Tiruchirappalli on September 17, 2026, for Low Power Fpga Based Alu Design Using Clock Gating Technique.
Inventors include Harshith Teella; Kodali Harshit Sai; and Dr. V. Manikandan.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: The invention at hand reveals a low power Arithmetic Logic Unit (ALU) designed on a Field Programmable Gate Array (FPGA) by one of a clock gating algorithm in order to reduce dynamic power spending. Most of the traditional FPGA-based designs operate by constantly switching the clock signal whether they are actively doing work or not hence results in an undue power-switching loss. The proposed system incorporates a clock gating control circuit which only enables the clock when an ALU operation is requested and disables the clock at idle states. The ALU assists in the most important arithmetic and logical operations including addition and subtraction and analogy logical operations with AND, OR, XOR, and comparison. Design is manipulated in hardware description format and created in standard FPGA. The invention also greatly enhances the energy consumption by minimizing the logical clock dividends, without affecting performance or operational validity. The suggested architecture will support standard FPGA tools, is scalable, and applicable to low-power embedded platform systems, portable technology, IoT technologies, and energy-efficient digital computing technology.
Disclaimer: Curated by HT Syndication.
