MUMBAI, India, Sept. 14 -- Intellectual Property India has published a patent application (202641103832 A) filed by Chennai Institute Of Technology on August 28, 2026, for Low-Power Filter Architecture For Portable Signal Processing Applications.
Inventors include Dr. S. Murugeswari Murthy; Dr. R. Mohandas; B. Maharaja; and S. Radhika.
The application for the patent was published on September 11, 2026, under issue no. 37/2026.
Abstract: Title: LOW-POWER FILTER ARCHITECTURE FOR PORTABLE SIGNAL PROCESSING APPLICATIONS The titled invention discloses a 16-bit MUX-XOR based Square Root Carry Select 5 Adder (SQRT CSLA) designed for low power consumption, reduced area, and reduced propagation delay. The Group 2, Group 3, Group 4, and Group 5 structures are formed using half adders instead of full adders, thereby reducing the number of logic gates and multiplexers. Selected multiplexer functions are replaced with XOR-based logic to further reduce hardware complexity and switching power. The proposed SQRT CSLA 10 is integrated into a Wallace tree multiplier, wherein partial products are generated using AND gates, reduction stages use half and full adders, and the proposed SQRT CSLA performs the final addition. The Wallace multiplier is further integrated into a Direct Form FIR filter comprising delay elements, multiplier units, and adder units. The proposed architecture provides reduced area, delay, and power consumption for 15 portable digital signal processing applications.
Disclaimer: Curated by HT Syndication.
