MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641114615 A) filed by Dayananda Sagar College Of Engineering on September 24, 2026, for Low Power Double Tail Dynamic Comparator In 90nm Cmos Technology For Biomedical Applications.
Inventors include Pranav Raghavendra Rao; Dr. Srividya B V; Dr. Rajesh Kumar; Ganesh K B; Dr. Jugul Kishor; Dr. Nagarathna; and Mr. Chetan Umadi.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: Double-Tail Dynamic Comparator (DTDC) designed and implemented in 90nm CMOS technology, operating at a supply voltage of 1.8V. The proposed comparator employs a two-stage architecture consisting of a pre-amplification stage followed by a regenerative latch stage. The design achieves a balanced optimization across three critical performance axes (power consumption, propagation delay, and input-referred noise) making it uniquely suitable for deployment as the core decision element in Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) intended for biomedical signal measurement systems. The comparator demonstrates an energy consumption of 28.76 fJ/cycle, an average propagation delay of 76.91ps, an input-referred noise resolution of 7.4685 µVrms. These parameters collectively position the invention as a high-performance, energy-efficient building block for wearable and implantable biomedical devices that must digitize weak physiological signals such as Electrocardiography (ECG) and Electroencephalography (EEG) waveforms reliably over extended battery lifetimes.
Disclaimer: Curated by HT Syndication.
